MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 370

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
8.3.2.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts
low and then goes high when the duty count is reached.
Read: Anytime
Write: Anytime
8.3.2.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Read: Anytime
Write: Anytime
370
PPOL[7:0]
Reset
Reset
Field
7–0
W
W
R
R
PPOL7
PCLK7
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
PWM Polarity Register (PWMPOL)
PWM Clock Select Register (PWMCLK)
0
0
7
7
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
reached.
reached.
PCLKL6
PPOL6
0
0
6
6
Figure 8-5. PWM Clock Select Register (PWMCLK)
Figure 8-4. PWM Polarity Register (PWMPOL)
Table 8-2. PWMPOL Field Descriptions
PPOL5
PCLK5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
PPOL4
PCLK4
NOTE
0
0
4
4
Description
PPOL3
PCLK3
0
0
3
3
PPOL2
PCLK2
0
0
2
2
PPOL1
PCLK1
Freescale Semiconductor
0
0
1
1
PPOL0
PCLK0
0
0
0
0