S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 145

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S9S12P128J0MFT

Manufacturer Part Number
S9S12P128J0MFT
Description
MCU 128K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12P128J0MFT

Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
S12
No. Of I/o's
34
Ram Memory Size
6KB
Cpu Speed
32MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 5-9
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
Freescale Semiconductor
Start of Bit Time
Start of Bit Time
Speedup Pulse
Target System
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
BKGD Pin
BKGD Pin
Perceived
Drive and
Perceived
Speedup
Drive to
Drive to
Pulse
Host
Host
shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
High-Impedance
S12P-Family Reference Manual, Rev. 1.13
10 Cycles
10 Cycles
R-C Rise
10 Cycles
10 Cycles
High-Impedance
Host Samples
High-Impedance
Host Samples
BKGD Pin
BKGD Pin
Background Debug Module (S12SBDMV1)
Speedup Pulse
High-Impedance
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of
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