S9S12P128J0MFT Freescale Semiconductor, S9S12P128J0MFT Datasheet - Page 113

• Manufacturer Part Number: S9S12P128J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P128J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Controller Family/series: S12
• No. Of I/o's: 34
• Ram Memory Size: 6KB
• Cpu Speed: 32MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The fixed 16KB page from 0x0000 to 0x3FFF is the page number 0x0C. Parts of this page are covered by
Registers, D-Flash and RAM space. See SoC Guide for details.
The fixed 16KB page from 0x4000–0x7FFF is the page number 0x0D.
The reset value of 0x0E ensures that there is linear Flash space available between addresses 0x0000 and
0xFFFF out of reset.
The fixed 16KB page from 0xC000-0xFFFF is the page number 0x0F.
3.4
The S12PMMC block performs several basic functions of the S12I sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1
Freescale Semiconductor
PIX[3:0]
•
•
Field
3–0
Normal single chip mode
This is the operation mode for running application codeThere is no external bus in this mode.
Special single chip mode
Functional Description
MCU Operating Modes
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 P-Flash or ROM
array pages is to be accessed in the Program Page Window.
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
Bit17
PPAGE Register [3:0]
S12P-Family Reference Manual, Rev. 1.13
Figure 3-8. PPAGE Address Mapping
Table 3-7. PPAGE Field Descriptions
Global Address [17:0]
Bit14
NOTE
Bit13
Description
Address: CPU Local Address
Address [13:0]
or BDM Local Address
Memory Map Control (S12PMMCV1)
Bit0
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