ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 91

• Manufacturer Part Number: ST10F272M-4TR3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
Note:
The bidirectional reset is not effective in case RPD is held low, when a software or watchdog
reset event occurs. On the contrary, if a software or watchdog bidirectional reset event is
active and RPD becomes low, the RSTIN pin is immediately released, while the internal
reset sequence is completed regardless of RPD status change (1024 TCL).
The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization
routine.
WDTCON flags
Similar to what is highlighted in the previous section, when discussing short reset and the
degeneration into long reset, comparable situations may occur when bidirectional reset is
enabled. The presence of the internal filter on RSTIN pin introduces a delay: When RSTIN is
released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it
remains still active (low) for a while. It means that depending on the internal clock speed, a
short reset may be recognized as a long reset: The WDTCON flags are set accordingly.
Moreover, when either software or watchdog bidirectional reset events occur, when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is
recognized high or low: 8TCL after the completion of the internal sequence, the level of
RSTF signal is sampled, and if recognized still low a hardware reset sequence starts, and
WDTCON will flag this last event, masking the previous one (software or watchdog reset).
Typically, a short hardware reset is recognized, unless the RSTIN pin (and consequently
internal signal RSTF) is sufficiently held low by the external hardware to inject a long
hardware reset. After this occurrence, the initialization routine is not able to recognize a
software or watchdog bidirectional reset event, since a different source is flagged inside
WDTCON register. This phenomenon does not occur when internal Flash is selected during
reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration
well beyond the filter delay.
Figures 27,
reset events: In particular
28
and
29
summarize the timing for software and watchdog timer bidirectional
Figure 29
shows the degeneration into hardware reset.
System reset
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