ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 169

• Manufacturer Part Number: ST10F272M-4TR3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
24.8.20.2 Slave mode
V
Table 75.
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
2. Formula for SSC clock cycle time: t
t
t
t
t
t
t
t
t
t
t
t
Symbol
310
311
312
313
314
315
316
317p
318p
317
318
DD
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after
checking that resulting timings are suitable for the master).
Where <SSCBR> represents the content of the SSC baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
= 5 V ±10 %, V
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
SR
SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
SSC slave mode timings
SS
Parameter
= 0 V, T
310
is 125ns (corresponding to 8 Mbaud).
(2)
A
310
= -40 to +125 °C, C
= 4 TCL * (<SSCBR> + 1)
(<SSCBR> = 0002h)
Maximum baudrate
Min
150
63
63
62
87
31
@ f
–
–
–
0
6
6.6 Mbaud
CPU
L
= 50 pF
= 40 MHz
(1)
Max
150
10
10
55
–
–
–
–
–
–
–
(<SSCBR> = 0001h - FFFFh)
4TCL + 12
6TCL + 12
t
t
2TCL + 6
310
310
8TCL
Min
Variable baudrate
/2 - 12
/2 - 12
–
–
–
0
6
Electrical characteristics
262144 TCL
2TCL + 30
Max
10
10
–
–
–
–
–
–
–
169/176
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns