ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 27

• Manufacturer Part Number: ST10F272M-4TR3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
5.2.3
Note:
Table 5
to the device user manual for more details on the memory mapping during bootstrap mode.
In particular, when bootstrap mode is entered:
●
●
●
●
In bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in
segment 0.
Example:
In default configuration, to program address 0, the user must put the value 01'0000h in the
FARL and FARH registers but to verify the content of the address 0, a read to 00'0000h must
be performed.
The next
be addressed by the CPU.
Table 6.
Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (t
Recovery time from power-down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
FCR1-0
FDR1-0
FAR
FER
FNVWPIR
FNVPIR-
Mirror
FNVAPR0
FNVAPR1
XFVTAUR0
Name
Test-Flash is seen and available for code fetches (address 00’0000h)
User IFlash is only available for read and write accesses
Write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever ROMS1 bit in SYSCON value
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
above refers to the configuration when bit ROMS1 of SYSCON register is set. Refer
Table 6
Control register interface
Flash control registers 1-0
Flash data registers 1-0
Flash address registers
Flash error register
Flash non-volatile protection i register
Mirror of Flash non-volatile protection i
register
Flash non-volatile access protection
register 0
Flash non-volatile access protection
register 1
X-bus Flash volatile temporary access
unprotection register 0
shows the control register interface composition: This set of registers can
Description
0x0008 0000 - 0x0008 0007
0x0008 0008 - 0x0008 000F
0x0008 0010 - 0x0008 0013
0x0008 0014 - 0x0008 0015
0x0008 DFB0 - 0x0008 DFB1
0x0008 DFB4 - 0x0008 DFB5
0x0008 DFB8 - 0x0008 DFB9
0x0008 DFBC - 0x0008 DFBF
0x0000 EB50 - 0x0000 EB51
Addresses
Internal Flash memory
PD
8 bytes
8 bytes
4 bytes
2 bytes
2 bytes
2 bytes
2 bytes
4 bytes
2 bytes
).
Size
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