ST10F272M-4TR3 STMicroelectronics, ST10F272M-4TR3 Datasheet - Page 55

• Manufacturer Part Number: ST10F272M-4TR3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
9.2
Exception and error traps list
Table 31
time.
Table 31.
1. - All the class B traps have the same trap number (and vector) and the same lower priority compared to the
Reset functions:
Hardware reset
Software reset
Watchdog timer overflow
Class A hardware traps:
Non-maskable interrupt
Stack overflow
Stack underflow
Class B hardware traps:
Undefined opcode
MAC interruption
Protected instruction fault
Illegal word operand access
Illegal instruction access
Illegal external bus access
Reserved
Software traps
TRAP instruction
class A traps and to the resets.
- Each class A trap has a dedicated trap number (and vector). They are prioritized in the second priority
level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
Exception condition
shows all of the possible exceptions or error conditions that can arise during run-
Trap priorities
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLBUS
STKOF
STKUF
ILLINA
Trap
NMI
flag
STOTRAP
STUTRAP
NMITRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
vector
Reset
Reset
Reset
Trap
[002Ch - 003Ch]
0000h – 01FCh
in steps of 4h
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
location
Vector
Any
[0Bh - 0Fh]
[00h - 7Fh]
number
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Any
00h
00h
00h
02h
04h
06h
Interrupt system
priority
Current
priority
Trap
CPU
III
III
III
55/176
II
II
II
I
I
I
I
I
I
(1)