STM32F103RET6TR STMicroelectronics, STM32F103RET6TR Datasheet - Page 13
![MCU ARM 32BIT 512KB FLASH 64LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
STM32F103RET6TR
Manufacturer Part Number
STM32F103RET6TR
Description
MCU ARM 32BIT 512KB FLASH 64LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F103VCT6.pdf
(123 pages)
Specifications of STM32F103RET6TR
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
For Use With
497-10508 - BOARD EVAL FOR MEMS SENSORS497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32KSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8511 - KIT STARTER FOR STM32 512K FLASH497-8505 - KIT STARTER FOR STM32F10XE MCU497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2MCBSTM32 - BOARD EVAL FOR STM STM32X SER497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F103RET6TR
Manufacturer:
ST
Quantity:
872
Company:
Part Number:
STM32F103RET6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F103xC, STM32F103xD, STM32F103xE
Figure 2.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
OSC32_OUT
OSC32_IN
OSC_OUT
64 MHz.
48 MHz or 72 MHz.
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
HSE OSC
Main
Clock Output
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
LSI
/2
RTCSEL[1:0]
/2
HSE
SYSCLK
PLLCLK
HSI
Doc ID 14611 Rev 7
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
72 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
Peripheral clock
enable
Peripheral clock
enable
/1, 1.5
USB
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
/1, 2, 4, 8, 16
If (APB2 prescaler =1) x1
TIM1 & 8 timers
Peripheral clock
enable
Peripheral clock
enable
/8
Prescaler
Prescaler
72 MHz max
APB2
APB1
Prescaler
/2, 4, 6, 8
Clock
/2
Enable (4 bits)
ADC
48 MHz
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
Legend:
I2S3CLK
I2S2CLK
Peripheral clock
enable
else x2
72 MHz max
else x2
36 MHz max
ADCCLK
Peripheral Clock
Peripheral Clock
Enable (20 bits)
Enable (15 bits)
USBCLK
to USB interface
Peripheral Clock
Enable (6 bits)
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to I2S3
to I2S2
to Cortex System timer
Peripheral Clock
Enable (2 bit)
To SDIO AHB interface
FSMCCLK
SDIOCLK
HCLK/2
to TIM2,3,4,5,6 and 7
TIMxCLK
TIMXCLK
peripherals to APB2
PCLK1
PCLK2
to APB1
peripherals
to ADC1, 2 or 3
to FSMC
Description
to TIM1 and TIM8
to SDIO
ai14752b
13/123