ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 58

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

Power saving modes
11.6.1
58/171
Figure 29. AWUFH mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
5. If the PLL is enabled by option byte, it outputs the clock after an additional delay of t
Register description
AWUFH control/status register (AWUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:3 = Reserved.
interrupt). Refer to
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
Figure
7
0
11).
0
Table 15: Interrupt mapping on page 47
0
(AWUCSR.AWUEN=1)
HALT INSTRUCTION
N
(Active-halt disabled)
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
1)
0
ENABLE
3)
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
AWU RC OSC
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
MAIN OSC
PERIPHERALS
CPU
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
I[1:0] BITS
I[1:0] BITS
N
CYCLE
for more details.
0
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
OFF
OFF
5)
ON
ON
ON
ON
ON
ON
10
AWU
4)
4)
F
STARTUP
AWUM
(see
ST7DALIF2
AWUEN
0