ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 34

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

Supply, reset and clock management
9.4
9.4.1
34/171
Figure 11. PLL output frequency timing diagram
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of t
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC
t
Refer to
Register description
Main clock control/status register (MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by hardware after a reset. This bit allows to
enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit selects the
input clock f
0: Normal mode (f
1: Slow mode (f
STAB
7
0
(see
Section 9.7.4 on page 44
Figure 11
OSC2
CPU =
0
or f
CPU =
4/8 x
input
freq.
OSC2
and
f
OSC2
t
f
STARTUP
OSC2
Section 20.3.3: Internal RC oscillator and PLL on page
STARTUP
/32.
/32)
0
t
.
LOCK
for a description of the LOCKED bit in the SICSR register.
0
LOCKED bit set
PLL
t
STAB
0
) is reached after a stabilization time of
0
t
MCO
ST7DALIF2
131)
SMS
0