ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 163

• Manufacturer Part Number: ST7FDALIF2M6
• Description: IC MCU 8BIT 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2131-5

ST7DALIF2
Note:
OPT3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a selected threshold as shown in
Table 97.
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated when entering Halt mode while the
Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Table 98.
See Clock Management Block diagram in
LVD Off
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
2.4 V - 3.3 V
3.3 V - 5.5 V
V
DD
range
LVD threshold configuration
List of valid option combinations
Internal RC 1%
External clock or
oscillator
(depending on OPT6:4
selection)
Internal RC 1%
External clock or
oscillator
(depending on OPT6:4
selection)
Clock source
Operating conditions
Configuration
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Figure 12
0.7 MHz @3 V
2.8 MHz @3 V
1 MHz @5 V
8 MHz @5 V
Typ f
0-4 MHz
0-8 MHz
4 MHz
8 MHz
-
-
-
-
CPU
OSC
0
0
1
1
0
0
1
1
-
-
-
-
Device configuration
Option bits
PLLOFF PLLx4x8
LVD1
1
1
0
0
1
0
1
0
1
0
1
0
-
-
-
-
Table
LVD0
97.
163/171
1
0
1
0
1
1
1
0
0
1
1
1
-
-
-
-