ST7FDALIF2M6 STMicroelectronics, ST7FDALIF2M6 Datasheet - Page 152
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ST7FDALIF2M6
Manufacturer Part Number
ST7FDALIF2M6
Description
IC MCU 8BIT 8K 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7DALI-EVAL.pdf
(171 pages)
Specifications of ST7FDALIF2M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4 bit
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2131-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
Electrical characteristics
Note:
152/171
1
2
Table 88.
1. Data based on design simulation and/or characterisation results, not tested in production.
2. Depends on f
Figure 89. SPI slave timing diagram with CPHA=0
Measurement points are done at CMOS levels: 0.3xV
When no communication is on-going the data output line of the SPI (MOSI in master mode,
MISO in slave mode) has its alternate function capability released. In this case, the pin
status depends on the I/O port configuration.
t
Symbol
t
t
t
su(SS)
h(SS)
w(SCKH)
t
w(SCKL)
t
t
t
t
t
dis(SO)
t
t
t
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
h(SI)
MISO
MOSI
SS
(1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
(1)
OUTPUT
INPUT
INPUT
SS setup time
SS hold time
SCK high and low
time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid
time
Data output hold time
Data output valid
time
Data output hold time
SPI characteristics (continued)
see note 2
CPU
Parameter
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
(2)
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable
edge)
Master (after enable
edge)
CPU
t
t
h(SI)
c(SCK)
= 8 MHz, then T
Conditions
t
v(SO)
BIT6 OUT
CPU
BIT1 IN
= 1/ f
t
(4 x T
h(SO)
DD
CPU
and 0.7xV
CPU
Min
100
100
100
100
100
120
= 125 ns and t
90
t
t
0
0
0
r(SCK)
f(SCK)
) +150
LSB IN
LSB OUT
DD
t
h(SS)
.
SU(SS)
Max
120
240
120
120
= 550 ns
t
dis(SO)
ST7DALIF2
note 2
see
Unit
ns