ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 79
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
I
12.4.5 Low Power Modes
12.4.6 Interrupts
Figure 46. Event Flags and Interrupt Generation
Note: The I
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
2
WAIT
HALT
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
C BUS INTERFACE (Cont’d)
Mode
*
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
ADD10
BERR
ARLO
ADSL
*
BTF
No effect on I
I
I
In HALT mode, the I
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
2
2
SB
AF
2
C interrupts cause the device to exit from WAIT mode.
C registers are frozen.
C interrupt events are connected to
2
C interface.
Interrupt Event
2
C interface is inactive and does not acknowledge data on the bus. The I
ITE
ST72104G, ST72215G, ST72216G, ST72254G
Description
STOPF
ADD10
ADSEL
Event
ARLO
BERR
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
INTERRUPT
EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
C interface
from
Exit
Halt
79/140
No
No
No
No
No
No
No
No