ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 125
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
14.11 COMMUNICATION INTERFACE CHARACTERISTICS
14.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 91. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
OSC
Symbol
1/t
t
t
w(SCKH)
t
w(SCKL)
t
t
t
t
t
t
t
dis(SO)
t
t
t
t
r(SCK)
f(SCK)
su(SS)
t
t
f
su(MI)
v(MO)
h(MO)
MISO
MOSI
h(SS)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
, and T
SCK
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
see note 2
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
t
t
h(SI)
c(SCK)
t
DD
v(SO)
DD
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
,
BIT6 OUT
ST72104G, ST72215G, ST72216G, ST72254G
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
Conditions
DD
BIT1 IN
.
t
f
f
h(SO)
CPU
CPU
=8MHz
=8MHz
t
t
r(SCK)
f(SCK)
f
CPU
LSB IN
0.0625
see I/O port pin description
0.25
0.25
Min
120
120
100
100
100
100
100
90
LSB OUT
0
0
0
/128
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
2
4
/4
/2
t
dis(SO)
125/140
Unit
t
MHz
CPU
ns
note 2
see