ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 34
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
10.4 LOW POWER MODES
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
10.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
34/140
WAIT
HALT
External interrupt on
selected external
event
D7
Mode
Interrupt Event
7
D6
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
D5
Event
D4
Flag
-
Description
D3
Control
Enable
DDRx
ORx
Bit
D2
from
Wait
Exit
Yes
D1
from
Halt
Exit
Yes
D0
0
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer deactivated)
1: Output push-pull (when available)
DD7
O7
7
7
DD6
O6
DD5
O5
DD4
O4
DD3
O3
DD2
O2
DD1
O1
DD0
O0
0
0