ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 260

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
IMPORTANT NOTES (Cont’d)
16.1.5 Header Time-out Does Not Prevent
Wake-up from Mute Mode
Normally, when LINSCI is configured in LIN slave
mode, if a header time-out occurs during a LIN
header reception (that is, header length > 57 bits),
the LIN Header Error bit (LHE) is set, an interrupt
occurs to inform the application but the LINSCI
should stay in mute mode, waiting for the next
header reception.
Problem Description
The LINSCI sampling period is Tbit / 16. If a LIN
Header time-out occurs between the 9th and the
15th sample of the Identifier Field Stop Bit (refer to
Figure
mode. Nevertheless, LHE is set and LIN Header
Detection Flag (LHDF) is kept cleared.
In addition, if LHE is reset by software before this
15th sample (by accessing the SCISR register and
Figure 153. Header Reception Event Sequence
260/265
153), the LINSCI wakes up from mute
LIN Synch
Break
LIN Synch
Field
T
HEADER
Identifier
Field
reading the SCIDR register in the LINSCI interrupt
routine), the LINSCI will generate another LINSCI
interrupt (due to the RDRF flag setting).
Impact on application
Software may execute the interrupt routine twice
after header reception.
Moreover, in reception mode, as the receiver is no
longer in mute mode, an interrupt will be generat-
ed on each data byte reception.
Workaround
The problem can be detected in the LINSCI inter-
rupt routine. In case of timeout error (LHE is set
and LHLR is loaded with 00h), the software can
check the RWU bit in the SCICR2 register. If RWU
is cleared, it can be set by software. Refer to
ure 154 on page
bold characters.
ID field STOP bit
Active mode is set
(RWU is cleared)
261. Workaround is shown in
Critical
Window
RDRF flag is set
Fig-