ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 115
ST72F561J4T6
Manufacturer Part Number
ST72F561J4T6
Description
IC MCU 8BIT 16K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F561K6T6.pdf
(265 pages)
Specifications of ST72F561J4T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F561J4T6
Manufacturer:
COILCRAFT
Quantity:
4 000
Company:
Part Number:
ST72F561J4T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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SERIAL PERIPHERAL INTERFACE (cont’d)
10.6.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 74. Data Clock Timing Diagram
74).
(from slave)
(from slave)
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA = 0
CPHA = 1
Bit 4
Bit 4
Bit 4
Bit 4
Figure 74
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit3
Bit3
Bit3
Bit3
shows an SPI transfer with the four com-
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSBit
LSBit
LSBit
LSBit
ST72561
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