ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 181

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

beCAN CONTROLLER (Cont’d)
10.9.4.4 Message Storage
The interface between the software and the hard-
ware for the CAN messages is implemented by
means of mailboxes. A mailbox contains all infor-
mation related to a message; identifier, data, con-
trol and status information.
Transmit Mailbox
The software sets up the message to be transmit-
ted in an empty transmit mailbox. The status of the
transmission is indicated by hardware in the
MCSR register.
Offset to Transmit
Mailbox base ad-
dress (bytes)
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Transmit Mailbox Mapping
Register Name
MCSR
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
Reserved
Reserved
Receive Mailbox
When a message has been received, it is available
to the software in the FIFO output mailbox. Once
the software has handled the message (e.g. read
it) the software must release the FIFO output mail-
box by means of the RFOM bit in the CRFR regis-
ter to make the next incoming message available.
The filter match index is stored in the MFMI regis-
ter.
Offset to Receive
Mailbox base ad-
dress (bytes)
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Receive Mailbox Mapping
Register Name
MFMI
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
Reserved
Reserved
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