ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 81

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
Table 12-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 12-7.
Table 12-8.
DIEOE
DIEOE
Signal
DIEOV
Signal
DIEOV
PUOE
DDOE
DDOV
PUOE
DDOE
DDOV
Name
PUOV
PVOE
PVOV
Name
PUOV
PVOE
PVOV
AIO
AIO
DI
DI
Figure 12-5 on page
and
SPI SLAVE OUTPUT
OC0/OC1C ENABLE
PB7/OC0A/OC1C
SPI MSTR INPUT
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PCINT3 • PCIE0
PCINT7 • PCIE0
PORTB3 • PUD
PCINT3 INPUT
PCINT7 INPUT
Table 12-8
SPE • MSTR
SPE • MSTR
SPE • MSTR
OC0/OC1C
PB3/MISO
0
1
–
0
0
0
0
1
–
relate the alternate functions of Port B to the overriding signals
76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
ATmega640/1280/1281/2560/2561
SPI MSTR OUTPUT
PCINT6 • PCIE0
SPI SLAVE INPUT
OC1B ENABLE
PCINT6 INPUT
PCINT2 • PCIE0
PORTB2 • PUD
PCINT2 INPUT
PB6/OC1B
SPE • MSTR
SPE • MSTR
SPE • MSTR
PB2/MOSI
OC1B
0
0
0
0
1
–
0
1
–
PCINT5 • PCIE0
OC1A ENABLE
PCINT5 INPUT
PCINT1 • PCIE0
PB5/OC1A
PORTB1 • PUD
PCINT1 INPUT
SCK OUTPUT
SPE • MSTR
SPE • MSTR
SPE • MSTR
SCK INPUT
OC1A
PB1/SCK
0
0
0
0
1
–
0
1
–
PCINT4 • PCIE0
OC2A ENABLE
PCINT4 INPUT
PCINT0 • PCIE0
PORTB0 • PUD
PCINT0 INPUT
SPE • MSTR
SPE • MSTR
PB4/OC2A
PB0/SS
OC2A
SPI SS
0
0
0
0
1
–
0
0
1
–
0
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