ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 328

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.6.14
2549M–AVR–09/10
ATmega640 Boot Loader Parameters
In
Self-Programming are given.
Table 28-7.
Note:
Table 28-7
Return:
Do_spm:
Wait_spm:
Wait_ee:
1
1
0
0
; return to RWW section
; verify that RWW section is safe to read
in
sbrs temp1, RWWSB
ret
; re-enable the RWW section
ldi
call Do_spm
rjmp Return
; check for previous SPM complete
in
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
The different BOOTSZ Fuse configurations are shown in
temp1, SPMCSR
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
temp1, SPMCSR
temp2, SREG
SPMCSR, spmcrval
SREG, temp2
1
0
1
0
through
Boot Size Configuration, ATmega640
words
words
words
words
1024
2048
4096
512
Table 28-9 on page
16
32
ATmega640/1280/1281/2560/2561
; If RWWSB is set, the RWW section is not ready yet
4
8
0x0000 -
0x7DFF
0x0000 -
0x7BFF
0x0000 -
0x77FF
0x0000 -
0x6FFF
329, the parameters used in the description of the
(Note:)
0x7E00 -
0x7FFF
0x7C00 -
0x7FFF
0x7800 -
0x7FFF
0x7000 -
0x7FFF
Figure 28-2 on page
0x7DFF
0x7BFF
0x77FF
0x6FFF
320.
0x7E00
0x7C00
0x7800
0x7000
328