ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 86

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

12.4
12.4.1
8151H–AVR–02/11
Register Description
SFIOR - Special Function IO Register
Table 12-21
shown in
Table 12-21. Overriding Signals for Alternate Functions in PG4:PG1
Table 12-22. Overriding Signals for Alternate Functions in PG0
• Bit 2 – PUD: Pull-up disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 66
Bit
Read/Write
Initial Value
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-6 on page
and
TSM
R/W
7
0
Table 12-22
PG4/TOSC1
AS0
0
AS0
0
0
0
AS0
0
–
T/C0 OSC INPUT
R
6
–
0
for more details about this feature.
relates the alternate functions of Port G to the overriding signals
71.
R
5
–
0
PG3/TOSC2
AS0
0
AS0
0
0
0
AS0
0
–
T/C0 OSC OUTPUT
R
4
–
0
ACME
R/W
3
0
PG0/WR
SRE
0
SRE
1
SRE
WR
0
0
–
–
PUD
R/W
2
0
PG2/ALE
SRE
0
SRE
1
SRE
ALE
0
0
–
–
ATmega128A
PSR0
R/W
1
0
PSR321
R/W
0
0
PG1/RD
SRE
0
SRE
1
SRE
RD
0
0
–
–
SFIOR
“Con-
86