ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 70

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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12.2.3
8151H–AVR–02/11
Digital Input Enable and Sleep Modes
Note:
As shown in
schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode, Power-save mode, Standby mode, and Extended Standby mode to avoid
high power consumption if some input signals are left floating, or have an analog signal level
close to V
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt
Request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari-
ous other alternate functions as described in
If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned sleep modes, as the clamping in these sleep modes produces the requested
logic change.
Assembly Code Example
C Code Example
unsigned char i;
:.
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
ldi
out
out
; Insert nop for synchronization
nop
; Read port pins
in
:.
:.
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
:.
1. For the assembly program, two temporary registers are used to minimize the time from pull-
CC
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
/2.
Figure
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
PORTB,r16
DDRB,r17
r16,PINB
(1)
12-2, the digital input signal can be clamped to ground at the input of the
(1)
“Alternate Port Functions” on page
ATmega128A
71.
70

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