ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 160

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

8151H–AVR–02/11
Table 17-2.
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting.
normal or CTC mode (non-PWM).
Table 17-3.
Table 17-4
mode.
Table 17-4.
Note:
Mode
COM21
0
1
2
3
COM21
0
0
1
1
0
0
1
1
The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. How-
ever, the functionality and location of these bits are compatible with previous versions of the timer.
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare
WGM21
Table 17-3
(CTC2)
match is ignored, but the set or clear is done at BOTTOM. See
for more details.
shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM
0
0
1
1
Waveform Generation Mode Bit Description
Compare Output Mode, Non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM20
COM20
0
1
0
1
WGM20
(PWM2)
0
1
0
1
shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on compare match, set OC2 at BOTTOM,
(non-inverting mode)
Set OC2 on compare match, clear OC2 at BOTTOM,
(inverting mode)
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on compare match
Clear OC2 on compare match
Set OC2 on compare match
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
(1)
TOP
0xFF
0xFF
OCR2
0xFF
“Fast PWM Mode” on page 154
Update of
OCR2 at
Immediate
TOP
Immediate
BOTTOM
ATmega128A
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
160