ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet - Page 223

• Manufacturer Part Number: ATMEGA128A-AU
• Description: MCU 8BIT 128K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4784435

Table 21-5.
8151H–AVR–02/11
Status Code
(TWSR)
Prescaler
Bits
are 0
$A8
$B0
$B8
$C0
$C8
Status of the Two-wire Serial Bus
and Two-wire Serial Interface
Hardware
Own SLA+R has been received;
ACK has been returned
Arbitration lost in SLA+R/W as
master; own SLA+R has been
received; ACK has been returned
Data byte in TWDR has been
transmitted; ACK has been
received
Data byte in TWDR has been
transmitted; NOT ACK has been
received
Last data byte in TWDR has been
transmitted (TWEA = “0”); ACK
has been received
Status Codes for Slave Transmitter Mode
Application Software Response
To/from TWDR
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
Load data byte
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
To TWCR
STA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
STO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TWIN
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWE
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be re-
ceived
Switched to the not addressed slave mode;
no recognition of own SLA or GCA
Switched to the not addressed slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode;
no recognition of own SLA or GCA
Switched to the not addressed slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
Next Action Taken by TWI Hardware
ATmega128A
223