DSPIC30F6015-20E/PT Microchip Technology, DSPIC30F6015-20E/PT Datasheet - Page 140
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DSPIC30F6015-20E/PT
Manufacturer Part Number
DSPIC30F6015-20E/PT
Description
IC DSPIC MCU/DSP 144K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6015-30IPT.pdf
(232 pages)
4.DSPIC30F6015-30IPT.pdf
(14 pages)
5.DSPIC30F6015-30IPT.pdf
(12 pages)
6.DSPIC30F6015-30IPT.pdf
(18 pages)
Specifications of DSPIC30F6015-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164315 - MODULE SKT MPLAB PM3 44TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
MICROCHIP
Quantity:
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DSPIC30F6015-20E/PT
Manufacturer:
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Quantity:
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MICROCHIP/微芯
Quantity:
20 000
dsPIC30F6010A/6015
20.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least one clock cycle.
Other trigger sources can come from timer modules,
motor control PWM module, or external interrupts.
20.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling
sequencing. The ADCBUF will not be updated with the
partially completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multichannel group conversion sequence.
DS70150D-page 140
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the A/D at the maximum
specified
Auto-Convert Trigger option should be
selected
Auto-Sample Time bits should be set to 1
T
will give a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger
will result in additional T
synchronize the external event to the A/D.
AD
(SAMC = 00001). This configuration
(SSRC = 111)
conversion
AD
.
speed,
AD
and
cycles to
AD
wait is
the
the
20.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 20-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
"Electrical Characteristics" for minimum T
other operating conditions.
Example 20-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 9
Selecting the A/D Conversion
Clock
T
ADCS<5:0> = 2
Actual T
AD
= T
ADCS<5:0> = 2
CY
AD
T
T
* (0.5 * (ADCS<5:0> + 1))
AD
CY
DD
= 2 •
= 4.09
=
=
= 99 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 84 nsec
= 33 nsec (30 MIPS)
© 2008 Microchip Technology Inc.
= 5V). Refer to Section 24.0
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(9 + 1)
. The source of the
– 1
– 1
AD
AD
.
AD
under
time