DSPIC30F6015-20E/PT Microchip Technology, DSPIC30F6015-20E/PT Datasheet - Page 109
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DSPIC30F6015-20E/PT
Manufacturer Part Number
DSPIC30F6015-20E/PT
Description
IC DSPIC MCU/DSP 144K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6015-30IPT.pdf
(232 pages)
4.DSPIC30F6015-30IPT.pdf
(14 pages)
5.DSPIC30F6015-30IPT.pdf
(12 pages)
6.DSPIC30F6015-30IPT.pdf
(18 pages)
Specifications of DSPIC30F6015-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
52
Flash Memory Size
144KB
Supply Voltage Range
2.5V To 5.5V
Package
64TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
52
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164315 - MODULE SKT MPLAB PM3 44TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
MICROCHIP
Quantity:
1 143
Company:
Part Number:
DSPIC30F6015-20E/PT
Manufacturer:
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Quantity:
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Microchip Technology
Quantity:
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Part Number:
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Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
17.0
The Inter-Integrated Circuit™ (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
This module offers the following key features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
17.1
The hardware fully implements all the master and
slave functions of the I
specifications, as well as 7 and 10-bit addressing.
Thus, the I
a master on an I
FIGURE 17-1:
© 2008 Microchip Technology Inc.
Note:
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
I
Operating Function Description
2
2
C™ MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
C module can operate either as a slave or
2
C bus.
bit 15
bit 15
PROGRAMMER’S MODEL
2
C Standard and Fast mode
2
C serial communication
2
C™) module provides
2
C port can be
bit 9
bit 8
bit 7
bit 7
dsPIC30F6010A/6015
17.1.1
The following types of I
• I
• I
• I
See the I
17.1.2
I
is data.
17.1.3
I2CCON and I2CSTAT are control and STATUS
registers, respectively. The I2CCON register is
readable and writable. The lower 6 bits of I2CSTAT are
read-only. The remaining bits of the I2CSTAT are
read/write.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CRCV is the receive buffer, as shown in Figure 16-1.
I2CTRN is the transmit register to which bytes are written
during a transmit operation, as shown in Figure 16-2.
The I2CADD register holds the slave address. A Status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the Baud Rate Generator reload
value.
In receive operations, I2CRSR and I2CRCV together
form a double-buffered receiver. When I2CRSR receives
a complete byte, it is transferred to I2CRCV and an
interrupt pulse is generated. During transmission, the
I2CTRN is not double-buffered.
2
C has a 2-pin interface; pin SCL is clock and pin SDA
Note:
2
2
2
C Slave operation with 7-bit address
C Slave operation with 10-bit address
C Master operation with 7 or 10-bit address
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
2
C programmer’s model in Figure 17-1.
VARIOUS I
PIN CONFIGURATION IN I
I
Following a Restart condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
2
C REGISTERS
I2CRCV (8 bits)
I2CTRN (8 bits)
I2CBRG (9 bits)
I2CCON (16 bits)
I2CSTAT (16 bits)
I2CADD (10 bits)
2
C operation are supported:
2
C MODES
DS70150D-page 109
2
C MODE