DSPIC30F5016-20E/PT Microchip Technology, DSPIC30F5016-20E/PT Datasheet - Page 86
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F5016-20E/PT
Manufacturer Part Number
DSPIC30F5016-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5016-30IPT.pdf
(230 pages)
4.DSPIC30F5016-30IPT.pdf
(14 pages)
5.DSPIC30F5016-30IPT.pdf
(6 pages)
6.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F5015/5016
13.1
Each output compare channel can select between one
of two 16-bit timers; Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the output compare module.
13.2
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple output compare
match modes:
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these compare match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
13.3
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is
configured for one of two dual output compare modes,
which are:
• Single Output Pulse mode
• Continuous Output Pulse mode
13.3.1
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
• Determine instruction cycle time T
• Calculate desired pulse width value based on T
• Calculate time to start pulse from timer start value
• Write pulse width start and stop times into OCxR
• Set Timer Period register to value equal to, or
• Set OCM<2:0> = 100.
• Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
DS70149D-page 86
of 0x0000.
and OCxRS Compare registers (x denotes
channel 1, 2, ...,N).
greater than, value in OCxRS Compare register.
Timer2 and Timer3 Selection Mode
Simple Output Compare Match
Mode
Dual Output Compare Match Mode
SINGLE-PULSE MODE
CY
.
CY
.
13.3.2
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
• Determine instruction cycle time T
• Calculate desired pulse value based on T
• Calculate timer to start pulse width from timer start
• Write pulse width start and stop times into OCxR
• Set Timer Period register to value equal to, or
• Set OCM<2:0> = 101.
• Enable timer, TON (TxCON<15>) = 1.
13.4
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is
configured for the PWM mode of operation. When
configured for the PWM mode of operation, OCxR is
the main latch (read-only) and OCxRS is the secondary
latch. This enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1.
2.
3.
4.
13.4.1
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again
configured for the PWM mode of operation, with the
additional feature of input Fault protection. While in this
mode, if a logic ‘0’ is detected on the OCFA pin, the
respective PWM output pin is placed in the
high-impedance
(OCxCON<4>) indicates whether a Fault condition has
occurred. This state will be maintained until both of the
following events have occurred:
• The external Fault condition has been removed.
• The PWM mode has been re-enabled by writing
value of 0x0000.
and OCxRS (x denotes channel 1, 2, ...,N)
Compare registers, respectively.
greater than, value in OCxRS Compare register.
to the appropriate control bits.
Set the PWM period by writing to the appropriate
Period register.
Set the PWM duty cycle by writing to the OCxRS
register.
Configure the output compare module for PWM
operation.
Set the TMRx prescale value and enable the
timer, TON (TxCON<15>) = 1.
Simple PWM Mode
CONTINUOUS PULSE MODE
INPUT PIN FAULT PROTECTION
FOR PWM
input
© 2008 Microchip Technology Inc.
state.
The
CY
.
OCFLT
CY
.
bit