DSPIC30F5016-20E/PT Microchip Technology, DSPIC30F5016-20E/PT Datasheet - Page 154
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F5016-20E/PT
Manufacturer Part Number
DSPIC30F5016-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5016-30IPT.pdf
(230 pages)
4.DSPIC30F5016-30IPT.pdf
(14 pages)
5.DSPIC30F5016-30IPT.pdf
(6 pages)
6.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5016-30IPT PDF datasheet #3
- DSPIC30F5016-30IPT PDF datasheet #4
- DSPIC30F5016-30IPT PDF datasheet #5
- DSPIC30F5016-30IPT PDF datasheet #6
- Current page: 154 of 230
- Download datasheet (4Mb)
dsPIC30F5015/5016
21.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least one clock
cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
21.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling
sequencing. The ADCBUF will not be updated with the
partially completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the next
channel converted. If simultaneous sampling is specified,
the A/D will continue with the next multichannel group
conversion sequence.
DS70149D-page 154
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the ADC at the maximum
specified
Auto-Convert Trigger option should be
selected
Auto-Sample Time bits should be set to 1
T
will give a total conversion period (sample
+ convert) of 13 T
The use of any other conversion trigger will
result
synchronize the external event to the ADC.
AD
(SAMC = 00001). This configuration
in
(SSRC
additional
conversion
AD
.
=
111)
T
AD
speed,
cycles
and
AD
wait is
the
the
to
21.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 21-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
“Electrical Characteristics” for minimum T
other operating conditions.
Example 21-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 21-1:
21.7
The dsPIC30F 10-bit ADC specifications permit a
maximum
summarizes the conversion speeds for the dsPIC30F
10-bit ADC and the required operating conditions.
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 5
Selecting the A/D Conversion
Clock
ADC Speeds
ADCS<5:0> = 2
T
Actual T
AD
1
= T
ADCS<5:0> = 2
Msps
CY
AD
T
T
* (0.5*(ADCS<5:0> +1))
AD
CY
DD
= 2 •
= 4.09
=
=
= 99 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 84 nsec
= 33 nsec (30 MIPS)
© 2008 Microchip Technology Inc.
= 5V). Refer to Section 24.0
sampling
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
- 1
AD
CY
AD
(9 + 1)
. The source of the
rate.
- 1
- 1
AD
Table 21-1
AD
.
AD
under
time
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