DSPIC30F5016-20E/PT Microchip Technology, DSPIC30F5016-20E/PT Datasheet - Page 103
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DSPIC30F5016-20E/PT
Manufacturer Part Number
DSPIC30F5016-20E/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5016-30IPT.pdf
(230 pages)
4.DSPIC30F5016-30IPT.pdf
(14 pages)
5.DSPIC30F5016-30IPT.pdf
(6 pages)
6.DSPIC30F5016-30IPT.pdf
(18 pages)
Specifications of DSPIC30F5016-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5016-30IPT PDF datasheet #3
- DSPIC30F5016-30IPT PDF datasheet #4
- DSPIC30F5016-30IPT PDF datasheet #5
- DSPIC30F5016-30IPT PDF datasheet #6
- Current page: 103 of 230
- Download datasheet (4Mb)
15.13 PWM Update Lockout
For a complex PWM application, the user may need to
write up to four Duty Cycle registers and the Time Base
Period register, PTPER, at a given time. In some appli-
cations, it is important that all buffer registers be written
before the new duty cycle and period values are loaded
for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit and clearing the IUE control bit in
the PWMCON2 SFR. The UDIS bit affects all Duty
Cycle Buffer registers and the PWM time base period
buffer, PTPER. No duty cycle changes or period value
changes will have effect while UDIS = 1.
If the IUE bit is set, any change to the Duty Cycle
registers is immediately updated regardless of the bit
state of the UDI. The PWM Period register update
(PTPER) is not affected by the IUE control bit.
15.14 PWM Special Event Trigger
The PWM module has a special event trigger that
allows A/D conversions to be synchronized to the PWM
time base. The A/D sampling and conversion time may
be programmed to occur at any point within the PWM
period. The special event trigger allows the user to
minimize the delay between the time when A/D conver-
sion results are acquired and the time when the duty
cycle value is updated.
The PWM special event trigger has an SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time base is in an Up/Down Counting
mode, an additional control bit is required to specify the
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the
special event trigger will occur on the upward counting
cycle of the PWM time base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time base. The SEVTDIR
control bit has no effect unless the PWM time base is
configured for an Up/Down Counting mode.
© 2008 Microchip Technology Inc.
15.14.1
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events:
• Any write to the SEVTCMP register
• Any device Reset
15.15 PWM Operation During CPU Sleep
The Fault A and Fault B input pins have the ability to
wake the CPU from Sleep mode. The PWM module
generates an interrupt if either of the Fault pins is
driven low while in Sleep.
15.16 PWM Operation During CPU Idle
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
dsPIC30F5015/5016
Mode
Mode
SPECIAL EVENT TRIGGER
POSTSCALER
DS70149D-page 103
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