ATMEGA162-16MU Atmel, ATMEGA162-16MU Datasheet - Page 3

• Manufacturer Part Number: ATMEGA162-16MU
• Description: IC AVR MCU 16K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
Block Diagram
2513K–AVR–07/09
The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega162
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
Figure 2. Block Diagram
VCC
GND
PORTA DIGITAL INTERFACE
PORTA DRIVERS/BUFFERS
INSTRUCTION
INSTRUCTION
AVR CPU
PROGRAMMING
CONTROL
PROGRAM
PROGRAM
REGISTER
DECODER
COUNTER
FLASH
LINES
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
LOGIC
+
-
PA0 - PA7
PB0 - PB7
REGISTERS
INTERFACE
PURPOSE
REGISTER
GENERAL
POINTER
STATUS
STACK
COMP.
SRAM
ALU
SPI
X
Y
Z
INTERFACE
PE0 - PE2
DRIVERS/
BUFFERS
DIGITAL
PORTE
PORTE
OSCILLATOR
WATCHDOG
INTERRUPT
COUNTERS
MCU CTRL.
INTERNAL
& TIMING
EEPROM
TIMERS/
USART0
USART1
PORTC DIGITAL INTERFACE
TIMER
PORTD DIGITAL INTERFACE
PORTC DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
UNIT
PC0 - PC7
PD0 - PD7
OSCILLATOR
CALIBRATED
OSCILLATOR
OSCILLATOR
INTERNAL
ATmega162/V
XTAL1
XTAL2
RESET
3