ATMEGA162-16MU Atmel, ATMEGA162-16MU Datasheet - Page 243

• Manufacturer Part Number: ATMEGA162-16MU
• Description: IC AVR MCU 16K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reading the
Calibration Byte
Parallel Programming
Characteristics
2513K–AVR–07/09
The algorithm for reading the calibration byte is as follows (refer to
page 237
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 102. Parallel Programming Timing, Including some General Timing Requirements
Figure 103. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
PAGEL
XTAL1
DATA
BS1
XA0
XA1
(DATA, XA0/1, BS1, BS2)
1. The timing requirements shown in
for details on Command and Address loading):
ing operation.
Data & Contol
ADDR0 (low byte)
LOAD ADDRESS
RDY/BSY
(LOW BYTE)
PAGEL
XTAL1
WR
t
t
BVPH
DVXH
LOAD DATA
(LOW BYTE)
DATA (low byte)
t
t
XHXL
PHPL
Figure 102
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
(i.e., t
t
BVWL
(HIGH BYTE)
LOAD DATA
DVXH
DATA (high byte)
t
WLWH
WLRL
t
XLPH
, t
LOAD DATA
XHXL
“Programming the Flash” on
, and t
ATmega162/V
t
PLXH
t
WLBX
XLDX
LOAD ADDRESS
) also apply to load-
(LOW BYTE)
ADDR1 (low byte)
t
WLRH
(1)
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