ATMEGA162-16MU Atmel, ATMEGA162-16MU Datasheet - Page 104

• Manufacturer Part Number: ATMEGA162-16MU
• Description: IC AVR MCU 16K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer/Counter0,
Timer/Counter1,
and
Timer/Counter3
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
104
ATmega162/V
Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler module, but
the Timer/Counters can have different prescaler settings. The description below applies to
Timer/Counter3, Timer/Counter1, and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the clock select logic of the
Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1, and Timer/Counter0. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the Timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the Timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024,
additional selections for Timer/Counter3: 32 and 64).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it
is connected to.
An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock
(clk
tem clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then
passed through the edge detector.
Tn/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of
the internal system clock (
clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 44. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
CLK_I/O
T1
/clk
Tn
/1024. In addition, Timer/Counter3 has the option of choosing f
clk
T
I/O
0) for Timer/Counter1 and Timer/Counter0. The Tn/T0 pin is sampled once every sys-
D
LE
CLK_I/O
Q
). Alternatively, one of four taps from the prescaler can be used as a
clk
Synchronization
D
I/O
). The latch is transparent in the high period of the internal system
Q
Figure 44
T1
/clk
T
0
shows a functional equivalent block diagram of the
pulse for each positive (CSn2:0 = 7) or negative
D
CLK_I/O
Q
/8, f
CLK_I/O
CLK_I/O
Edge Detector
/16 and f
/64, f
CLK_I/O
2513K–AVR–07/09
Tn_sync
(To Clock
Select Logic)
CLK_I/O
/256, or
/32.