ATMEGA162-16MU Atmel, ATMEGA162-16MU Datasheet - Page 168

• Manufacturer Part Number: ATMEGA162-16MU
• Description: IC AVR MCU 16K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AVR USART vs. AVR
UART – Compatibility
Clock Generation
168
ATmega162/V
The USART is fully compatible with the AVR UART regarding:
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However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
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The following control bits have changed name, but have same functionality and register location:
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The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using synchronous mode.
Figure 76
Figure 76. Clock Generation Logic, Block Diagram
Signal description:
Bit locations inside all USART Registers
Baud Rate Generation
Transmitter Operation
Transmit Buffer Functionality
Receiver Operation
A second Buffer Register has been added. The two buffer registers operate as a circular
FIFO buffer. Therefore the UDR must only be read once for each incoming data! More
important is the fact that the Error Flags (FE and DOR) and the ninth data bit (RXB8) are
buffered with the data in the receive buffer. Therefore the status bits must always be read
before the UDR Register is read. Otherwise the error status will be lost since the buffer state
is lost.
The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
received data to remain in the serial Shift Register (see
full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun
(DOR) error conditions.
CHR9 is changed to UCSZ2.
OR is changed to DOR.
DDR_XCK
XCK
Pin
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/ 2
/ 4
Figure
75) if the Buffer Registers are
/ 2
DDR_XCK
U2X
0
1
0
1
2513K–AVR–07/09
0
1
1
0
UMSEL
txclk
rxclk