AT32UC3B0128-A2UR Atmel, AT32UC3B0128-A2UR Datasheet - Page 266
![MCU AVR32 128K FLASH 64-TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0128-A2UR
Manufacturer Part Number
AT32UC3B0128-A2UR
Description
MCU AVR32 128K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0128-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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20.7.1.1
20.7.1.2
32059J–12/2010
Clock divider
Transmitter clock management
Figure 20-4. Divided Clock Block Diagram
The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is
4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190.
The divided clock is provided to both the receiver and transmitter. When this field is written to
zero, the clock divider is not used and remains inactive.
When CMR.DIV is written to a value equal to or greater than one, the divided clock has a fre-
quency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a
duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the
divided clock regardless of whether the CMR.DIV value is even or odd.
Figure 20-5.
Table 20-2.
The transmitter clock is generated from the receiver clock, the divider clock, or an external clock
scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit
Maximum
CLK_SSC / 2
Divided Clock
Divided Clock
Range of Clock Divider
CLK_SSC
CLK_SSC
Divided Clock Generation
DIV = 3
DIV = 1
CLK_SSC
/ 2
Divided Clock Frequency = CLK_SSC/2
Divided Clock Frequency = CLK_SSC/6
Clock Divider
12-bit Counter
Minimum
CLK_SSC / 8190
CMR
Divided Clock
AT32UC3B
266
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