AT32UC3B0128-A2UR Atmel, AT32UC3B0128-A2UR Datasheet - Page 264
![MCU AVR32 128K FLASH 64-TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0128-A2UR
Manufacturer Part Number
AT32UC3B0128-A2UR
Description
MCU AVR32 128K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0128-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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20.5
20.6
20.6.1
20.6.2
20.6.3
20.7
32059J–12/2010
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Clocks
Interrupts
Table 20-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SSC before disabling the clock, to avoid freezing the SSC in an undefined state.
The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt
requires the interrupt controller to be programmed first.
This chapter contains the functional description of the following: SSC functional block, clock
management, data framing format, start, transmitter, receiver, and frame sync.
The receiver and the transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when transmis-
sion starts. Alternatively, this can be done by programming the transmitter to use the receive
clock and/or to start a data transfer when reception starts. The transmitter and the receiver can
be programmed to operate with the clock signals provided on either the TX_CLOCK or
RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maxi-
mum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.
Pin Name
RX_FRAME_SYNC
RX_CLOCK
RX_DATA
TX_FRAME_SYNC
TX_CLOCK
TX_DATA
I/O Lines Description
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
Type
Input/Output
Input/Output
Input
Input/Output
Input/Output
Output
AT32UC3B
264
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