AT32UC3B0128-A2UR Atmel, AT32UC3B0128-A2UR Datasheet - Page 245
AT32UC3B0128-A2UR
Manufacturer Part Number
AT32UC3B0128-A2UR
Description
MCU AVR32 128K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0128-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.13.7
19.13.7.1
Figure 19-29. Repeated Start + Reversal from Read to Write Mode
19.13.7.2
Figure 19-30. Repeated Start + Reversal from Write to Read Mode
32059J–12/2010
TWI_RHR
TWI_RHR
TWI_THR
TWI_THR
TXCOMP
TXCOMP
EOSACC
EOSACC
SVREAD
SVREAD
RXRDY
RXRDY
SVACC
SVACC
TXRDY
TXRDY
TWD
TWD
Reversal after a Repeated Start
Reversal of Read to Write
Reversal of Write to Read
S
S
As soon as a START is detected
As soon as a START is detected
SADR
SADR
The master initiates the communication by a read command and finishes it by a write command.
Figure 19-29 on page 245
Note:
The master initiates the communication by a write command and finishes it by a read com-
mand.Figure 19-30 on page 245
mode.
W
R
Read TWI_RHR
A
A
DATA0
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is
detected again.
DATA0
DATA0
A
A
DATA0
DATA1
DATA1
DATA1
describes the repeated start + reversal from Read to Write mode.
NA
A
describes the repeated start + reversal from Write to Read
DATA1
Sr
Sr
SADR
SADR
Cleared after read
Cleared after read
R
W
DATA2
A
A
DATA2
DATA2
DATA2
A
A
DATA3
AT32UC3B
DATA3
DATA3
DATA3
NA
A
P
P
245
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