ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 38
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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9.3
9.4
9.5
9.6
8021G–AVR–03/11
BOD Disable
Idle Mode
ADC Noise Reduction Mode
Power-down Mode
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses,
the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it
is possible to disable the BOD by software for some of the sleep modes, see
37. The sleep mode power consumption will then be at the same level as when BOD is globally
disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately
after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again.
This ensures safe operation in case the V
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60
µs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
”MCUCR – MCU Control Register” on page
vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active,
i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI
start condition detection, Timer/Counter2, LCD Controller, and the Watchdog to continue operat-
ing (if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an LCD controller interrupt, USI start condition interrupt, a Timer/Counter2 interrupt, an
SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can
wake up the MCU from ADC Noise Reduction mode.
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the
CPU
and clk
FLASH
42.
, while allowing the other clocks to run.
CC
42. Writing this bit to one turns off the BOD in rele-
level has dropped during the sleep period.
I/O
, clk
ATmega329P/3290P
CPU
, and clk
Table 27-3 on page
FLASH
, while allowing the
Table 9-1 on page
”MCUCR –
297,
38
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