ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 241
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.5
23.5.1
8021G–AVR–03/11
Register Description
LCDCRA – LCD Control and Status Register A
• Bit 7 – LCDEN: LCD Enable
Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned
off immediately. Turning the LCD Controller/Driver off while driving a display, enables ordinary
port function, and DC voltage can be applied to the display if ports are configured as output. It is
recommended to drive output to ground if the LCD Controller/Driver is disabled to discharge the
display.
• Bit 6 – LCDAB: LCD Low Power Waveform
When LCDAB is written logic zero, the default waveform is output on the LCD pins. When
LCDAB is written logic one, the Low Power Waveform is output on the LCD pins. If this bit is
modified during display operation the change takes place at the beginning of a new frame.
• Bit 5 – Reserved Bit
This bit is reserved and will always read as zero.
• Bit 4 – LCDIF: LCD Interrupt Flag
This bit is set by hardware at the beginning of a new frame, at the same time as the display data
is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I-bit in SREG
are set. LCDIF is cleared by hardware when executing the corresponding Interrupt Handling
Vector. Alternatively, writing a logical one to the flag clears LCDIF. Beware that if doing a Read-
Modify-Write on LCDCRA, a pending interrupt can be disabled. If Low Power Waveform is
selected the Interrupt Flag is set every second frame.
• Bit 3 – LCDIE: LCD Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the LCD Start of Frame Interrupt is
enabled.
• Bit 2 – LCDBD: LCD Buffer Disable
The intermediate voltage levels in the LCD are generated by an internal resistive voltage divider
and passed through buffer to increase the current driving capability. By writing this bit to one the
buffers are turned off and bypassed, resulting in decreased power consumption. The total resis-
tance of the voltage divider is nominally 400 kΩ between LCDCAP and GND.
• Bit 1 – LCDCCD: LCD Contrast Control Disable
Writing this bit to one disables the internal power supply for the LCD driver. The desired voltage
must be applied to the LCDCAP pin from an external power supply. To avoid conflict between
internal and external power supply, this bit must be written as '1' prior to or simultaneously with
writing '1' to the LCDEN bit.
Bit
(0xE4)
Read/Write
Initial Value
LCDEN
R/W
7
0
LCDAB
R/W
6
0
R
5
–
0
LCDIF
R/W
4
0
LCDIE
R/W
3
0
ATmega329P/3290P
LCDBD
R
2
0
LCDCCD
R
1
0
LCDBL
R/W
0
0
LCDCRA
241
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