ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 260
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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25.5.3
8021G–AVR–03/11
Scanning the Clock Pins
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 25-5
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
Figure 25-5. Boundary-scan Cells for Oscillators and Clock Options
Table 25-2
XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 25-2.
Notes:
Enable Signal
EXTCLKEN
OSCON
OSC32EN
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
shows how each Oscillator with external connection is supported in the scan chain.
summaries the scan registers for the external clock pin XTAL1, oscillators with
Scan Signals for the Oscillator
Previous
From
Cell
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
ShiftDR
0
1
ClockDR
D
UpdateDR
Q
Next
Cell
To
D
G
Q
EXTEST
0
1
XTAL1/TOSC1
External Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
Clock Option
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
ATmega329P/3290P
Previous
From
Cell
ShiftDR
0
1
ClockDR
D
FF1
Scanned Clock Line
Q
Next
Cell
when not Used
To
To System Logic
0
1
1
260
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