ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 22
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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7.6
7.6.1
7.6.2
7.6.3
8021G–AVR–03/11
Register Description
EEPROM Read/Write Access
EEARH and EEARL – EEPROM Address Register ATmega329P/3290P
EEDR – EEPROM Data Register
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section “7.4.2” on page 20.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15:10 – Reserved
These bits are reserved and will always read as zero.
• Bits 9:0 – EEAR[9:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
CC
EEAR7
R/W
is likely to rise or fall slowly on power-up/down. This causes the device for some
15
MSB
R
0
X
R/W
–
7
7
0
EEAR6
R/W
14
R
X
–
6
0
R/W
6
0
EEAR5
R/W
13
R
X
–
5
0
for details on how to avoid problems in these situations.
R/W
5
0
EEAR4
R/W
12
R
–
4
0
X
R/W
4
0
EEAR3
R/W
11
R
X
–
3
0
Table
R/W
3
0
EEAR2
R/W
R/W
ATmega329P/3290P
10
X
X
–
2
7-1. A self-timing function, however,
R/W
2
0
EEAR9
EEAR1
R/W
R/W
X
9
1
X
R/W
1
0
EEAR8
EEAR0
R/W
R/W
8
0
X
X
LSB
R/W
EEARH
EEARL
0
0
EEDR
22
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