ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 175
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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19.3.4
19.4
8021G–AVR–03/11
Frame Formats
Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Figure 19-4. Synchronous Mode XCK Timing.
The UCPOLn bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 19-5
optional.
Figure 19-5. Frame Formats
UCPOL = 1
UCPOL = 0
illustrates the possible combinations of the frame formats. Bits inside brackets are
(IDLE)
RxD / TxD
RxD / TxD
St
XCK
XCK
0
Figure 19-4
1
2
shows, when UCPOLn is zero the data will be changed at
3
4
FRAME
[5]
[6]
[7]
ATmega329P/3290P
[8]
[P]
Sample
Sample
Sp1 [Sp2]
(St / IDLE)
175
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