ATMEGA3290P-20AUR Atmel, ATMEGA3290P-20AUR Datasheet - Page 15
![MCU AVR 32K FLASH 20MHZ 64TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA3290P-20AUR
Manufacturer Part Number
ATMEGA3290P-20AUR
Description
MCU AVR 32K FLASH 20MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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6.6.1
6.7
8021G–AVR–03/11
Instruction Execution Timing
SPH and SPL – Stack pointer High and Stack Pointer Low
This section describes the general access timing concepts for instruction execution. The
Atmel
source for the chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
2nd Instruction Execute
®
3rd Instruction Execute
1st Instruction Execute
AVR
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
®
CPU is driven by the CPU clock clk
The Parallel Instruction Fetches and Instruction Executions
SP15
R/W
R/W
SP7
15
7
0
0
clk
CPU
SP14
R/W
R/W
SP6
14
6
0
0
SP13
R/W
R/W
SP5
13
5
0
0
T1
SP12
R/W
R/W
SP4
12
4
0
0
CPU
, directly generated from the selected clock
T2
SP11
R/W
R/W
SP3
11
3
0
0
ATmega329P/3290P
SP10
SP2
R/W
R/W
10
2
0
0
T3
SP9
SP1
R/W
R/W
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
T4
SPH
SPL
15
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