ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 86

• Manufacturer Part Number: ATMEGA32U2-MU
• Description: MCU AVR USB 32K FLASH IND 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2.5 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.2.3
13.2.4
13.2.5
13.2.6
7799D–AVR–11/10
EIMSK – External Interrupt Mask Register
EIFR – External Interrupt Flag Register
PCICR – Pin Change Interrupt Control Register
PCIFR – Pin Change Interrupt Flag Register
• Bits 7:0 – INT[7:0]: External Interrupt Request 7:0 Enable
When an INT[7:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External
Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is acti-
vated on rising or falling edge or level sensed. Activity on any of these pins will trigger an
interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
• Bits 7:0 – INTF[7:0]: External Interrupt Flags 7:0
When an edge or logic change on the INT[7:0] pin triggers an interrupt request, INTF[7:0]
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT[7:0] in
EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
These flags are always cleared when INT[7:0] are configured as level interrupt. Note that when
entering sleep mode with the INT[3:0] interrupts disabled, the input buffers on these pins will be
disabled. This may cause a logic change in internal signals which will set the INTF[3:0] flags.
See
• Bit 1:0 – PCIE[1:0]: Pin Change Interrupt Enable 1:0
When the PCIE1/0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), Pin
Change interrupt 1/0 is enabled. Any change on any enabled PCINT[12:8]/[7:0] pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the
PCI1/0 Interrupt Vector. PCINT[12:8]/[7:0] pins are enabled individually by the PCMSK1/0
Register.
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
Bit
(0x68)
Read/Write
Initial Value
Bit
0x1B (0x3B)
Read/Write
Initial Value
“Digital Input Enable and Sleep Modes” on page 71
INTF7
INT7
R/W
R/W
7
0
7
0
R
R
7
0
7
0
-
-
INTF6
INT6
R/W
R/W
6
0
6
0
R
R
6
0
6
0
-
-
INTF5
INT5
R/W
R/W
5
0
5
0
R
R
5
–
0
5
–
0
INTF4
INT4
R/W
R/W
4
0
4
0
R
R
4
–
0
4
–
0
ATmega8U2/16U2/32U2
INTF3
INT3
R/W
R/W
3
0
3
0
R
R
3
–
0
3
–
0
for more information.
INTF2
INT2
R/W
R/W
2
0
2
0
R
R
2
–
0
2
–
0
INTF1
INT1
PCIE1
R/W
R/W
PCIF1
R/W
R/W
1
0
1
0
1
0
1
0
INTF0
IINT0
R/W
R/W
PCIE0
PCIF0
R/W
R/W
0
0
0
0
0
0
0
0
EIMSK
EIFR
PCICR
PCIFR
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