ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 204
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 204 of 309
- Download datasheet (6Mb)
21.13.1.1
21.13.2
7799D–AVR–11/10
Example with 1 OUT data bank
RXOUTI
RXOUTI
FIFOCON
FIFOCON
Example with 2 OUT data banks
OUT
OUT
Detailed description
“Manual” mode
(to bank 0)
(to bank 0)
DATA
DATA
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in
accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the current bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture,
HW
HW
ACK
ACK
SW
SW
read data from CPU
OUT
BANK 0
NAK
read data from CPU
BANK 0
(to bank 1)
DATA
SW
OUT
ACK
ATmega8U2/16U2/32U2
(to bank 0)
DATA
HW
SW
HW
ACK
SW
read data from CPU
BANK 1
SW
read data from CPU
BANK 0
204
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