ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 81
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 81 of 309
- Download datasheet (6Mb)
7799D–AVR–11/10
Table 12-10. Overriding Signals for Alternate Functions PD7..PD4
Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure.
PD3/INT3/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT3 ENABLE
1
INT3 INPUT
–
PD7/T0/INT7/
HBW/CTS
CTS
PORTD7 •
PUD
CTS
0
0
0
INT7/CTS
ENABLE
1
T0 INPUT
INT7 INPUT
CTS INPUT
–
PD6/INT6/
RTS
RTS
0
RTS
1
RTS
OUTPUT
ENABLE
RTS
OUTPUT
INT6
ENABLE
1
INT6 INPUT
–
PD2/INT2/RXD1/
AIN1
RXEN1
PORTD2 • PUD
RXEN1
0
0
0
INT2 ENABLE
AIN1 ENABLE
AIN1 ENABLE
INT2 INPUT/RXD1
AIN1 INPUT
PD5/XCK/PCINT12
0
0
0
0
XCK OUTPUT ENABLE
XCK1 OUTPUT
PCINT12 ENABLE
1
XCK INPUT
PCINT12 INPUT
–
ATmega8U2/16U2/32U2
PD1/INT1/AIN0
0
0
0
0
0
0
INT1 ENABLE
AIN0 ENABLE
AIN0 ENABLE
INT1 INPUT
AIN0 INPUT
(1)
PD0/INT0/OC0B
0
0
0
0
OC0B ENABLE
OC0B
INT0 ENABLE
1
INT0 INPUT
–
PD4/INT5
0
0
0
0
0
0
INT5
ENABLE
1
INT5 INPUT
–
81
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