ATMEGA645A-MUR Atmel, ATMEGA645A-MUR Datasheet - Page 50

• Manufacturer Part Number: ATMEGA645A-MUR
• Description: IC MCU AVR 64K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3
10.3.1
10.4
50
Watchdog Timer
Internal Voltage Reference
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Voltage Reference Enable Signals and Start-up Time
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P features an inter-
nal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an
input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2...0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P resets and exe-
cutes from the Reset Vector. For timing details on the Watchdog Reset, refer to
page
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 10-1. Refer to
”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 51
details.
Table 10-1.
WDTON
Unprogrammed
Programmed
ACBG bit in ACSR).
54.
Table 10-2 on page
WDT Configuration as a Function of the Fuse Settings of WDTON
CC
Safety
Level
= 5V. See characterization data for typical values at other V
1
2
”System and Reset Characteristics” on page
54. The WDR – Watchdog Reset – instruction resets the Watch-
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
326. To save power, the
How to Change Time-
out
Timed sequence
Timed sequence
Table 10-2 on
8285B–AVR–03/11
CC
levels. By
for