ATMEGA645A-MUR Atmel, ATMEGA645A-MUR Datasheet - Page 250

• Manufacturer Part Number: ATMEGA645A-MUR
• Description: IC MCU AVR 64K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24-3.
250
Signal Name
PRECH
SCTEST
ST
VCCREN
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Boundary-scan Signals for the ADC
Direction as seen
from the ADC
Input
Input
Input
Input
Note:
If the ADC is not to be used during scan, the recommended input values from
page 248
scan. Switch-Cap based differential amplifier requires fast operation and accurate timing which
is difficult to obtain when used in a scan chain. Details concerning operations of the differential
amplifier is therefore not provided.
The AVR ADC is based on the analog circuitry shown in
sive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measured within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
• The port pin for the ADC channel in use must be configured to be an input with pull-up disabled
• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
(Sample mode).
1. Incorrect setting of the switches in
Description
Precharge output latch of
comparator. (Active low)
Switch-cap TEST enable. Output
from differential amplifier is sent out
to Port Pin having ADC_4
Output of differential amplifier will
settle faster if this signal is high first
two ACLK periods after AMPEN
goes high.
Selects Vcc as the ACC reference
voltage.
should be used. The user is recommended not to use the Differential Amplifier during
may damage the part. There are several input choices to the S&H circuitry on the negative
input of the output comparator in
selected from either one ADC pin, Bandgap reference source, or Ground.
The lower limit is:
The upper limit is:
(1)
(Continued)
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
Figure 24-9 on page
⋅
Figure 24-9 on page 248
⋅
Recommended
Input when not
in Use
⋅
⋅
1
0
0
0
⁄
⁄
Figure 24-9 on page 248
=
=
248. Make sure only one path is
291
323
Output Values when
recommended inputs are Used,
and CPU is not Using the ADC
CC
=
=
will make signal contention and
.
0x123
0x143
1
0
0
0
Table 24-3 on
with a succes-
8285B–AVR–03/11