PIC16F819-I/ML Microchip Technology, PIC16F819-I/ML Datasheet - Page 592

• Manufacturer Part Number: PIC16F819-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F819-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details

PICmicro MID-RANGE MCU FAMILY
30.18
DS31030A-page 30-22
Param.
No.
62
63
64
65
66
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
§
RD7:RD0
tested.
This specification ensured by design.
RE1/WR
RE0/RD
RE2/CS
Note: Refer to
TdtV2wrH
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
Symbol
Example Parallel Slave Port (PSP) Timing Waveforms and Requirements
Figure 30-1
Data in valid before WR or CS
(setup time)
WR or CS to data–in invalid
(hold time)
RD and CS to data–out valid
RD or CS to data–out invalid
Inhibit of the IBF flag bit being cleared from
WR or CS
Figure 30-8:
Table 30-20:
for load conditions.
64
Example Parallel Slave Port Requirements
Characteristic
Example Parallel Slave Port Timing Waveforms
65
PIC16CXXX
PIC16LCXXX
Min
20
20
35
—
10
—
Typ†
—
—
—
—
—
—
62
3Tcy
1997 Microchip Technology Inc.
Max
63
80
30
—
—
—
§
Units Conditions
ns
ns
ns
ns
ns