PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 412

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
Timing Diagrams and Specifications
DS39770C-page 412
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 46
Type-A in 1/2 MUX, 1/2 Bias Drive .......................... 176
Type-A in 1/2 MUX, 1/3 Bias Drive .......................... 178
Type-A in 1/3 MUX, 1/2 Bias Drive .......................... 180
Type-A in 1/3 MUX, 1/3 Bias Drive .......................... 182
Type-A in 1/4 MUX, 1/3 Bias Drive .......................... 184
Type-A/Type-B in Static Drive .................................. 175
Type-B in 1/2 MUX, 1/2 Bias Drive .......................... 177
Type-B in 1/2 MUX, 1/3 Bias Drive .......................... 179
Type-B in 1/3 MUX, 1/2 Bias Drive .......................... 181
Type-B in 1/3 MUX, 1/3 Bias Drive .......................... 183
Type-B in 1/4 MUX, 1/3 Bias Drive .......................... 185
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 378
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
External Clock Requirements .................................. 376
I
I
Internal RC Accuracy ............................................... 377
MSSP I
MSSP I
2
2
C Bus Data Requirements (Slave Mode) .............. 387
C Bus Start/Stop Bits Requirements
(INTRC to HSPLL) ........................................... 300
PRI_RUN Mode ................................................. 46
PRI_RUN Mode (HSPLL) .................................. 45
(CCP1, CCP2) ................................................. 381
Requirements ................................................... 390
Requirements ................................................... 390
(Slave Mode, CKE = 0) .................................... 384
Requirements (CKE = 1) .................................. 385
(Slave Mode) .................................................... 386
(Master Mode, CKE = 0) ................................. 382
(Master Mode, CKE = 1) ................................. 383
2
2
C Bus Data Requirements ......................... 389
C Bus Start/Stop Bits Requirements .......... 388
Top-of-Stack Access .......................................................... 65
TSTFSZ ........................................................................... 345
Two-Speed Start-up ................................................. 291, 300
Two-Word Instructions
V
V
Voltage Reference Specifications .................................... 373
Voltage Regulator (On-Chip) ........................................... 299
W
Watchdog Timer (WDT) ........................................... 291, 297
WCOL ...................................................... 223, 224, 225, 228
WCOL Status Flag ................................... 223, 224, 225, 228
WWW Address ................................................................ 413
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 345
XORWF ........................................................................... 346
DDCORE
PLL Clock ................................................................ 377
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
Example Cases .......................................................... 69
Brown-out Reset (BOR) ........................................... 300
Low-Voltage Detection (LVD) .................................. 299
Operation in Sleep Mode ......................................... 300
Power-up Requirements .......................................... 300
Associated Registers ............................................... 298
Control Register ....................................................... 297
During Oscillator Failure .......................................... 301
Programming Considerations .................................. 297
/V
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 379
Requirements .................................................. 380
CAP
Pin .......................................................... 299
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