PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 406

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
Flash Program Memory ...................................................... 87
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 326
H
Hardware Multiplier ............................................................ 97
I
I/O Ports ........................................................................... 115
I
DS39770C-page 406
2
C Mode (MSSP) ............................................................ 200
Associated Registers ................................................. 95
Control Registers ....................................................... 88
Erase Sequence ........................................................ 92
Erasing ....................................................................... 92
Operation During Code-Protect ................................. 95
Reading ...................................................................... 91
Table Pointer
Table Pointer Boundaries .......................................... 90
Table Reads and Table Writes .................................. 87
Write Sequence ......................................................... 93
Writing ........................................................................ 93
Introduction ................................................................ 97
Operation ................................................................... 97
Performance Comparison .......................................... 97
Input Voltage Considerations ................................... 115
Open-Drain Outputs ................................................. 116
Output Pin Drive ....................................................... 115
Pin Capabilities ........................................................ 115
Pull-up Configuration ............................................... 116
Acknowledge Sequence Timing ............................... 228
Associated Registers ............................................... 234
Baud Rate Generator ............................................... 221
Bus Collision
Clock Arbitration ....................................................... 222
Clock Stretching ....................................................... 214
Clock Synchronization and the CKP Bit ................... 215
Effects of a Reset ..................................................... 229
General Call Address Support ................................. 218
I
Master Mode ............................................................ 219
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 229
Operation ................................................................. 205
Read/Write Bit Information (R/W Bit) ............... 205, 207
Registers .................................................................. 200
2
C Clock Rate w/BRG ............................................. 221
EECON1 and EECON2 ..................................... 88
TABLAT (Table Latch) Register ......................... 90
TBLPTR (Table Pointer) Register ...................... 90
Boundaries Based on Operation ........................ 90
Unexpected Termination .................................... 95
Write Verify ........................................................ 95
During a Repeated Start Condition .................. 232
During a Stop Condition ................................... 233
10-Bit Slave Receive Mode (SEN = 1) ............. 214
10-Bit Slave Transmit Mode ............................. 214
7-Bit Slave Receive Mode (SEN = 1) ............... 214
7-Bit Slave Transmit Mode ............................... 214
Baud Rate Generator ....................................... 221
Operation ......................................................... 220
Reception ......................................................... 225
Repeated Start Condition Timing ..................... 224
Start Condition Timing ..................................... 223
Transmission .................................................... 225
and Arbitration .................................................. 229
INCF ................................................................................ 326
INCFSZ ............................................................................ 327
In-Circuit Debugger .......................................................... 303
In-Circuit Serial Programming (ICSP) ...................... 291, 303
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 352
Indirect Addressing ............................................................ 81
INFSNZ ............................................................................ 327
Initialization Conditions for all Registers ...................... 57–59
Instruction Cycle ................................................................ 68
Instruction Set .................................................................. 305
Serial Clock (SCK/SCL) ........................................... 207
Slave Mode .............................................................. 205
Sleep Operation ....................................................... 229
Stop Condition Timing ............................................. 228
and Standard PIC18 Instructions ............................. 352
Clocking Scheme ....................................................... 68
Flow/Pipelining ........................................................... 68
ADDLW .................................................................... 311
ADDWF .................................................................... 311
ADDWF (Indexed Literal Offset Mode) .................... 353
ADDWFC ................................................................. 312
ANDLW .................................................................... 312
ANDWF .................................................................... 313
BC ............................................................................ 313
BCF ......................................................................... 314
BN ............................................................................ 314
BNC ......................................................................... 315
BNN ......................................................................... 315
BNOV ...................................................................... 316
BNZ ......................................................................... 316
BOV ......................................................................... 319
BRA ......................................................................... 317
BSF .......................................................................... 317
BSF (Indexed Literal Offset Mode) .......................... 353
BTFSC ..................................................................... 318
BTFSS ..................................................................... 318
BTG ......................................................................... 319
BZ ............................................................................ 320
CALL ........................................................................ 320
CLRF ....................................................................... 321
CLRWDT ................................................................. 321
COMF ...................................................................... 322
CPFSEQ .................................................................. 322
CPFSGT .................................................................. 323
CPFSLT ................................................................... 323
DAW ........................................................................ 324
DCFSNZ .................................................................. 325
DECF ....................................................................... 324
DECFSZ .................................................................. 325
Extended Instructions .............................................. 347
General Format ........................................................ 307
GOTO ...................................................................... 326
INCF ........................................................................ 326
INCFSZ .................................................................... 327
INFSNZ .................................................................... 327
IORLW ..................................................................... 328
IORWF ..................................................................... 328
Addressing ....................................................... 205
Addressing Masking ........................................ 206
Reception ........................................................ 207
Transmission ................................................... 207
Considerations when Enabling ........................ 352
Syntax .............................................................. 347
Use with MPLAB IDE Tools ............................. 354
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